update slides

example/example.typ

@@ -26,26 +26,23 @@
 
 #slide()[
   = Intel Press Workshops June 2017 #ftnt(link("https://www.techpowerup.com/235092/intel-says-amd-epyc-processors-glued-together-in-official-slide-deck", "TechPowerUp; no primary source available"))
-  #align(center, image(width: 79%, "./figures/intel_slide1.jpg"))
+
+  #v(1cm)
+  #align(center, image(width: 100%, "./figures/intel_slide1.jpg"))
 ]
 
 #slide()[
   = Why chiplets?
   #v(2cm)
 
-  #grid(
-    columns: (40%, 60%),
-    [
-      #v(2cm)
-        - Moore's Law 
-        - more flexibility in design
-        #pause
-        - low production yield for monolithic dies  \
-          #sym.arrow.r \$\$\$
-    ],
+  - Moore's Law 
+  - more flexibility in design
+  #pause
+  - low production yield for monolithic dies  \
+    #sym.arrow.r \$\$\$
 
-    [
- #let nm = ("45" + nm, "32" + nm, "28" + nm, "20" + nm, "14" + nm, "10" + nm, "7"+nm, "5" + nm)
+  #v(2cm)
+  #let nm = ("45" + nm, "32" + nm, "28" + nm, "20" + nm, "14" + nm, "10" + nm, "7"+nm, "5" + nm)
   #figure(
     canvas(length: 1.5cm, {
       plot.plot(size: (10, 4),
@@ -70,40 +67,45 @@
     }), 
     caption: [Normalized cost per chip vs. technology node, based on Naffziger et al.#ftnt(cite(form: "full", <Naffziger2021>))])
 
-    ]
-  )
-
 ]
 
 #slide()[
 = AMD Naples (1#super[st] Gen. EPYC) -- NUMA Toplogy #ftnt(link("https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56308-numa-topology-for-epyc-naples-family-processors.pdf"))
   #v(1cm)
-  #figure(image(width: 85%, "./figures/naples.jpg"))
+  #figure(image(width: 100%, "./figures/naples.jpg"))
 ]
 
 #slide()[
 = AMD Naples (1#super[st] Gen. EPYC) 
-  #figure(image(width: 60%, "./figures/naples-multilayerpackaging.jpg"), 
+  #figure(image(width: 90%, "./figures/naples-multilayerpackaging.jpg"), 
   caption: [Multi-layer package routing, DDR (red), IO (orange), infinity-fabric (blue) #ftnt(cite(form: "full", <Naffziger2021>))])
 ]
 
 #slide()[
 = AMD Rome (2#super[nd] Gen. EPYC) #ftnt(link("https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/amd-epyc-7002-tg-hpc-56827.pdf"))
-  #figure(image(width: 41%, "./figures/rome.jpg"))
+  #v(1cm)
+  #figure(image(width: 55%, "./figures/rome.jpg"))
 ]
 
 #slide()[
   = Memory Access Latencies for Naples and Rome, Naffziger et al.#ftnt(cite(form: "full", <Naffziger2020>))
   #v(1cm)
   #align(center, 
-      image(width: 85%, "./figures/naples-vs-rome.jpg")
+      image(width: 100%, "./figures/naples-vs-rome.jpg")
   )
 ]
 
 #slide()[
   = Impact of NUMA on Applications
-  == Emmerich et al. #ftnt(cite(form: "full", <Emmerich2018>)) -- User Space Networking Drivers
 
+  #v(2cm)
+  #figure(image(width: 100%, "./figures/userspacenetworkingdrivers.png"))
+]
+
+#slide()[
+  = Impact of NUMA on Applications
+  == Emmerich et al. #ftnt(cite(form: "full", <Emmerich2018>)) -- User Space Networking Drivers
+  #v(2cm)
   #figure(
     tablex(
       columns: 5,
@@ -125,26 +127,36 @@
       hlinex()
 
     ),
-  caption: [Forwarding performance, columns indicates pinning of resources, based on Emmerich et al.#cite(<Emmerich2018>)]
+  caption: [Forwarding performance in packets per second, columns indicates pinning of each resource, based on Emmerich et al. #cite(<Emmerich2018>)]
   )
 ]
 
 #slide()[
   = Impact of NUMA on Applications
-  == Li et al. #ftnt(cite(form: "full", <Li2014>)) -- Memcached
 
+  #v(2cm)
+  #figure(image(width: 100%, "./figures/talesoftail.png"))
+]
+
+#slide()[
+  = Impact of NUMA on Applications
+  == Li et al. #ftnt(cite(form: "full", <Li2014>)) -- Memcached
+  #v(2cm)
   #figure(
-    image(width: 60%, "./figures/talesoftail.png"),
-    caption: [Memcached tail latency; 2 sockets; two instances (green), one instance (blue), based on Li et al.#cite(<Li2014>)]
+    image(width: 60%, "./figures/talesoftail_diagram.png"),
+    caption: [Memcached tail latency; 2 sockets; two instances (green), one instance (blue), \ 
+    based on Li et al. #cite(<Li2014>)]
   )
 ]
 
 #slide()[
   = Conclusion
   #v(2cm)
-  - CPU architecture matters
+
   - Chiplet technology is a fundamental part of future CPU architectures
   - Inconsistent memory access latencies are a challenge for applications
+  - CPU architecture matters
+
 ]
 
 #slide()[