update slides
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#slide()[
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= Intel Press Workshops June 2017 #ftnt(link("https://www.techpowerup.com/235092/intel-says-amd-epyc-processors-glued-together-in-official-slide-deck", "TechPowerUp; no primary source available"))
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#align(center, image(width: 79%, "./figures/intel_slide1.jpg"))
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#v(1cm)
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#align(center, image(width: 100%, "./figures/intel_slide1.jpg"))
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]
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#slide()[
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= Why chiplets?
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#v(2cm)
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#grid(
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columns: (40%, 60%),
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[
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#v(2cm)
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- Moore's Law
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- more flexibility in design
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#pause
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- low production yield for monolithic dies \
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#sym.arrow.r \$\$\$
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],
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[
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#v(2cm)
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#let nm = ("45" + nm, "32" + nm, "28" + nm, "20" + nm, "14" + nm, "10" + nm, "7"+nm, "5" + nm)
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#figure(
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canvas(length: 1.5cm, {
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@ -71,39 +68,44 @@
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caption: [Normalized cost per chip vs. technology node, based on Naffziger et al.#ftnt(cite(form: "full", <Naffziger2021>))])
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]
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)
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]
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#slide()[
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= AMD Naples (1#super[st] Gen. EPYC) -- NUMA Toplogy #ftnt(link("https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56308-numa-topology-for-epyc-naples-family-processors.pdf"))
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#v(1cm)
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#figure(image(width: 85%, "./figures/naples.jpg"))
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#figure(image(width: 100%, "./figures/naples.jpg"))
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]
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#slide()[
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= AMD Naples (1#super[st] Gen. EPYC)
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#figure(image(width: 60%, "./figures/naples-multilayerpackaging.jpg"),
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#figure(image(width: 90%, "./figures/naples-multilayerpackaging.jpg"),
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caption: [Multi-layer package routing, DDR (red), IO (orange), infinity-fabric (blue) #ftnt(cite(form: "full", <Naffziger2021>))])
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]
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#slide()[
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= AMD Rome (2#super[nd] Gen. EPYC) #ftnt(link("https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/amd-epyc-7002-tg-hpc-56827.pdf"))
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#figure(image(width: 41%, "./figures/rome.jpg"))
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#v(1cm)
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#figure(image(width: 55%, "./figures/rome.jpg"))
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]
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#slide()[
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= Memory Access Latencies for Naples and Rome, Naffziger et al.#ftnt(cite(form: "full", <Naffziger2020>))
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#v(1cm)
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#align(center,
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image(width: 85%, "./figures/naples-vs-rome.jpg")
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image(width: 100%, "./figures/naples-vs-rome.jpg")
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)
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]
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#slide()[
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= Impact of NUMA on Applications
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== Emmerich et al. #ftnt(cite(form: "full", <Emmerich2018>)) -- User Space Networking Drivers
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#v(2cm)
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#figure(image(width: 100%, "./figures/userspacenetworkingdrivers.png"))
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]
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#slide()[
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= Impact of NUMA on Applications
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== Emmerich et al. #ftnt(cite(form: "full", <Emmerich2018>)) -- User Space Networking Drivers
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#v(2cm)
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#figure(
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tablex(
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columns: 5,
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@ -125,26 +127,36 @@
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hlinex()
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),
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caption: [Forwarding performance, columns indicates pinning of resources, based on Emmerich et al.#cite(<Emmerich2018>)]
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caption: [Forwarding performance in packets per second, columns indicates pinning of each resource, based on Emmerich et al. #cite(<Emmerich2018>)]
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)
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]
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#slide()[
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= Impact of NUMA on Applications
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== Li et al. #ftnt(cite(form: "full", <Li2014>)) -- Memcached
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#v(2cm)
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#figure(image(width: 100%, "./figures/talesoftail.png"))
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]
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#slide()[
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= Impact of NUMA on Applications
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== Li et al. #ftnt(cite(form: "full", <Li2014>)) -- Memcached
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#v(2cm)
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#figure(
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image(width: 60%, "./figures/talesoftail.png"),
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caption: [Memcached tail latency; 2 sockets; two instances (green), one instance (blue), based on Li et al.#cite(<Li2014>)]
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image(width: 60%, "./figures/talesoftail_diagram.png"),
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caption: [Memcached tail latency; 2 sockets; two instances (green), one instance (blue), \
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based on Li et al. #cite(<Li2014>)]
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)
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]
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#slide()[
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= Conclusion
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#v(2cm)
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- CPU architecture matters
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- Chiplet technology is a fundamental part of future CPU architectures
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- Inconsistent memory access latencies are a challenge for applications
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- CPU architecture matters
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]
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#slide()[
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example/figures/talesoftail_diagram.png
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example/figures/talesoftail_diagram.png
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example/figures/userspacenetworkingdrivers.png
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example/figures/userspacenetworkingdrivers.png
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@ -2,7 +2,7 @@
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#import "tumcolor.typ": *
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#let tum-theme(
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aspect-ratio: "16-9",
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aspect-ratio: "4-3",
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footer: [],
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background: white,
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foreground: black,
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@ -44,7 +44,7 @@
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]
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logo
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place(bottom+right, dx: 1cm, dy: 2cm)[
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place(bottom+right, dx: 1cm, dy: 2.5cm)[
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#image("../figures/TUM_Uhrenturm.png", fit: "stretch")
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]
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